Toward the implementation of analog LDPC decoders for long codewords

Error control codes are used in virtually every digital communication system. Traditionally, decoders have been implemented digitally. Analog decoders have been recently shown to have the potential to outperform digital decoders in terms of area and power/speed ratio. Analog designers have attempted to fully understand and exploit this potential for large decoders. However, large codes are generally still implemented with digital circuits. Nevertheless, in this thesis a number of aspects of analog decoder implementation are investigated with the hope of enabling the design of large analog decoders. In this thesis, we study and modify analog circuits used in a decoding algorithm known as the sum-product algorithm for implementation in a CMOS 90 nm technology. We apply a current-mode approach at the input nodes of these circuits and show through simulations that the power/speed ratio will be improved. Interested in studying the dynamics of decoders, we model an LDPC code in MATLAB's Simulink. We then apply the linearization technique on the modeled LDPC code in order to linearize the decoder about an initial state as its solution point. Challenges associated with decoder linearization are discussed. We also design and implement a chip comprised of the sum-product circuits with different configurations and sizes in order to study the effect of mismatch on the accuracy of the outputs. Unfortunately, testing of the chip fails as a result of errors in either the packaging process or fabrication

Energy-Efficient Wake-up Receivers for 915-MHz ISM Band Applications

Wake-up receiver (WuRx) is a well-known approach for optimizing the latency and power consumption of ultra-low power transceivers in wireless sensor nodes. Tuned RF (TRF) or Envelope Detection architecture is an appropriate topology for short-range Wireless Body Area Network (WBAN) applications, where achieving a very high sensitivity is not a priority. However, the demand for an improved sensitivity gets emphasized for longer transmission ranges. Regardless of the application, considering the existing trade-off between the power and sensitivity, design techniques and novel architectures are usually employed to optimize the power-sensitivity product. Moreover, considering the negative impact of higher data rate on the sensitivity, the energy-sensitivity product can be a more reasonable figure of merit when comparing WuRx designs. In this thesis, the RF-subsampling architecture has been combined with the TRF receiver architecture as a first approach for improving the power-sensitivity product. The overall power consumption is reduced as a result of employing the subsampling topology with a low-frequency local oscillator (LO). Post layout simulations show that the proposed WuRx draws only 56 μA from a 0.5 V supply and exhibits an input sensitivity of -70 dBm for a data rate of 100 kbps. The chip occupies an area of 0.15 mm2 and is fabricated with TSMC 90nm CMOS technology. Another major contribution of this work is to propose and implement a novel dual-mode ultra-low-power WuRx based on the subsampling topology, which not only reduces the overall power consumption but also optimizes the energy-sensitivity product of the receiver. During the typical mode of operation known as the Monitoring (MO) mode, the start frame bits are received at a rate of as low as 10 kbps. Having received the true preamble bits in the MO mode, the remaining wake-up pattern bits are received at a higher rate of 200 kbps during the Identifier (ID) mode. By lowering the gain of the front-end amplifier in the MO mode, the power dissipation is reduced, which in turn causes an increase in the overall noise figure of the receiver. However, adequate sensitivity and hence an optimized energy-sensitivity product is maintained by intentionally lowering the data rate as well as the detection bandwidth of the receiver in the MO mode. The proposed wake-up receiver has been designed and fabricated in IBM 130 nm technology with a core size of about 0.2 mm2 for the target frequency range of 902-928 MHz. The measured results show that the proposed dual-mode receiver achieves a sensitivity of -78.5 dBm and -75 dBm while dissipating an average power of 16.4 µW and 22.9 µW during MO and ID modes, respectively

A 14-GHz Bang-Bang Digital PLL with Sub-150-fs Integrated Jitter for Wireline Applications in 7-nm FinFET CMOS

Demands for increased wireline data throughput necessitate multi-gigahertz clock sources of ever-greater fidelity. This article demonstrates a 14-GHz bang-bang digital phase-locked loop (BBPLL) with 143-fs rms jitter (integrated from 1 kHz to 100 MHz) to clock a 56-Gb/s PAM-4 transceiver. The low jitter is achieved with an LC-based digitally controlled oscillator (DCO) having a tuning range of 2 GHz, a frequency resolution of 1.2 MHz/LSB, and a low phase noise of -104 dBc/Hz at 1-MHz offset. All PLL digital functions are consolidated in a single, fully synthesized digital signal processing unit operating at 3.5 GHz or 10 $\times$ the reference clock frequency. Limit cycles are minimized without the aid of a time-to-digital converter through substantial reduction of loop latency using a look-ahead digital loop filter. Various design techniques exploiting the advanced 7-nm FinFET technology are discussed, including noise reduction and tank ${Q}$ enhancement. Closed-loop phase noise performance is accurately predicted using an industry-standard digital event-driven simulator with dramatically reduced computation effort compared to analog or mixed-mode simulators. Here, the accuracy and computational burden of calculating 1/ ${f}^{\alpha }$ noise is overcome by pre-calculating the DCO and reference phase noise profiles. The results obtained from these simulation techniques show very close agreement with experimental measurements. This 7-nm FinFET PLL occupies a competitive 0.06 mm2 and consumes 40 mW